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Ordering number : ENA0844A
LV8092GQ
Overview
Bi-CMOS LSI
Piezo Actuator Driver IC
The LV8092GQ is a piezoelectric actuator driver IC. It internally generates drive waveforms and this makes it possible to control piezoelectric actuators with simple instructions.
Features
* Actuators using piezoelectric elements can be driven simply by I2C communication. * The piezoelectric drive waveforms are set externally by serial input signals using the I2C interface. * The rising and falling timings are determined with clock count. * EN input that controls the startup/stop of the IC. * The time for which the actuator is driven is determined with the drive frequency setting based on I2C communication. * Provides a busy signal output during periods when the actuator is being driven by OUT pin output so that applications can be aware of the actuator operating/stopped state. * Built-in thermal protection and undervoltage protection circuits
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Supply voltage Signal system supply voltage Output current Input signal voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max VDD max IO max VIN max Pd Topr Tstg *Mounted on a specified board. Conditions Ratings -0.5 to 6.0 -0.5 to 6.0 300 -0.5 to VDD+0.5 700 -30 to +85 -55 to +150 Unit V V mA V mW C C
* Specified board : 50mmx40mmx0.8mm, 4-layer glass epoxy circuit board.
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83107 MS / 71807 MS PC 20070402-S00001 No.A0844-1/12
LV8092GQ
Allowable Operating Conditions at Ta = 25C, GND = 0V
Parameter Supply voltage Signal system supply voltage Input signal voltage Maximum operating frequency Symbol VCC VDD VIN Ct max Conditions Ratings 2.5 to 3.3 1.6 to 3.3 0 to VDD Set STP count x 512 Unit V V V Times
Electrical Characteristics at Ta = 25C, VCC = 2.8V, GND = 0V, unless otherwise specified.
Parameter Standby mode current drain Operating mode current drain High-level input voltage Low-level input voltage CLK, TEST pin high-level input voltage CLK, TEST pin low-level input voltage Low voltage detection voltage Thermal protection temperature Output block upper-side on resistance Output block lower-side on resistance Turn on time Turn off time TPLH TPHL With no load *2 With no load *2 0.2 0.2 S S RonN 1.0 1.5 Vres TSD RonP VCC voltage *1 2.1 150 2.25 180 1.0 2.4 210 1.5 V C VIL2 CLK, TEST1/2 0 0.1xVDD V Symbol ICC0 ICC1 VIH VIL VIH2 Conditions min No CLK input, When EN = L CLK = 10MHz, When EN = H 1.6V VDD 3.3V EN, SCL, SDA, RESET 1.6V VDD 3.3V EN, SCL, SDA, RESET CLK, TEST1/2 0.8xVDD 0 0.5xVCC 0.7 Ratings typ max 1.0 1.5 VDD 0.2xVDD VCC A mA V V V Unit
*1 : Design guaranteed value (no measurement is performed) *2 : Rising time from 10 to 90% and falling time from 90 to 10% are specified with regard to the OUT pin voltage.
Package Dimensions
unit : mm (typ) 3341
0.8
Pd max -- Ta
Specified board : 50.0x40.0x0.8mm3 4-layer glass epoxy
Allowable power dissipation, Pd max - W
TOP VIEW 2.6
SIDE VIEW
BOTTOM VIEW (0.125)
0.7 0.6
(0.13)
(C0.116)
2.6
0.4 0.36
0.4
16 0.5 0.25 2 1 (0.55)
0.2
0.6
SIDE VIEW
0 - 20
0
20
40
60
80 85
100
(0.035)
Ambient temperature, Ta - C
SANYO : UCT16(2.6X2.6)
No.A0844-2/12
LV8092GQ
Pin Assignment
VCC 16 BUSY 1 (NC) 15 (NC) 14 VDD 13 12 TEST2
OUT2
2 (TOP VIEW)
11 GND
REG
3
10 EN
OUT1
4 5 TEST1 6 CLK 7 SCL 8 SDA
9
RESET
Block Diagram
VCC OUT1
OUT2
RFG
BUSY
TEST1 Thermal protection circuit Startup control block Piezoelectric drive waveform generation register Output control TEST2
I2C interface Level shifter VDD GND EN CLK SCL SDA RESET Microcontroller input voltage
Value of the resistor connected to the RFG pin Inrush current flowing to the piezoelectric elements can be controlled in the LV8092GQ by inserting a resistor between the RFG pin and GND potential. Since the resistance affects the actuator operation, the constant must be determined in a range from 0 to 3.3 while monitoring the operation of the actuator. Capacitor on the VCC line Piezoelectric actuators are capacitive loads in electrical terms, and they operate units by charging and discharging the charges. Since the charge between the capacitor on the VCC line and piezoelectric elements is transferred, the capacitor must be mounted near the VCC pin. The capacitance of the capacitor required is determined by the capacitance of the piezoelectric element. A capacitance within a range that does not affect operation must be selected.
No.A0844-3/12
LV8092GQ
Serial Bus Communication Specifications I2C serial transfer timing conditions
twH SCL twL th2 SDA th1 ts2 ts1 ts3 th1 tbuf
Start condition ton tof
Resend start condition
Stop condition
Input waveform condition
Standard mode
Parameter SCL clock frequency Data setup time symbol fscl ts1 ts2 ts3 Data hold time th1 th2 Pulse width twL twH Input waveform conditions ton tof Bus free time tbuf SCL clock frequency Setup time of SCL with respect to the falling edge of SDA Setup time of SDA with respect to the rising edge of SCL Setup time of SCL with respect to the rising edge of SDA Hold time of SCL with respect to the rising edge of SDA Hold time of SDA with respect to the falling edge of SCL SCL low period pulse width SCL high period pulse width SCL/SDA (input) rising time SCL/ SDA (input) falling time Interval between stop condition and start condition Conditions min 0 4.7 250 4.0 4.0 0 4.7 4.0 4.7 typ max 100 1000 300 unit kHz s ns s s s s s ns ns s
High-speed mode
Parameter SCL clock frequency Data setup time Symbol fscl ts1 ts2 ts3 Data hold time th1 th2 Pulse width twL twH Input waveform conditions ton tof Bus free time tbuf Conditions Clock frequency of SCL Setup time of SCL with respect to the falling edge of SDA Setup time of SDA with respect to the rising edge of SCL Setup time of SCL with respect to the rising edge of SDA Hold time of SCL with respect to the rising edge of SDA Hold time of SDA with respect to the falling edge of SCL SCL low period pulse width SCL high period pulse width SCL/SDA (input) rise time SCL/SDA (input) fall time Interval between the stop condition and the start condition 1.3 min 0 0.6 100 0.6 0.6 0 1.3 0.6 300 300 typ max 400 unit kHz s ns s s s s s ns ns s
No.A0844-4/12
LV8092GQ
I2C bus transfer method Start and stop conditions The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a data transfer operation.
SCL
SDA ts2 th2
When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is started when SDA is changed from high to low while SCL and SDA are high. Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is high.
Start condition Stop condition
SCL
SDA th1 th3
Data transfer and acknowledgement response After the start condition is generated, data is transferred one byte (8 bits) at a time. Any number of data bytes can be transferred consecutively. An ACK signal is sent to the sending side from the receiving side every time 8 bits of data are transferred. The transmission of an ACK signal is performed by setting the receiving side SDA to low after SDA at the sending side is released immediately after the clock pulse of SCL bit 8 in the data transferred has fallen low. After the receiving side has sent the ACK signal, if the next byte transfer operation is to receive only the byte, the receiving side releases SDA on the falling edge of the 9th clock of SCL. There are no CE signals in the I2C bus ; instead, a 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave address and to the command (R/W) which specifies the direction of subsequent data transfer. The LB8092GQ is a drive IC with a dedicated write function and it does not have a read function. The 7-bit address is transferred in sequence starting with MSB, and the eighth bit is set to low. The second and subsequent bytes are transferred in write mode. In the LV8092GQ, the slave address is stipulated to be "1110010.".
Start
M S B
Slave address
L S B
W
A C K
M S B
Register address
L S B
A C K
M S B
Data
L S B
A C K
Stop
SCL
SDA
111
010
1
000
000
10
000
100
01
No.A0844-5/12
LV8092GQ
Serial Map
Register Address A7 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 x 0 0 x 0 0 x 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 D7 M/I 0 GATE 0 0 x 0 0 x 0 0 D6 D5 D4 Data D3 DRVPULSE [6 : 0] 0 0 0 0 INIT 0 D2 D1 D0
CKSEL [1 : 0] 0 0
RET [1 : 0] 0 0
RST [7 : 0] 0 0 0 0 0
GTAS [7 : 0] 0 0 0 0 0
GTBR [7 : 0] 0 0 0 0 0
GTBS [7 : 0] 0 0 0 0 0
STP [7 : 0] 0 x 0 0 0 0 0 0
INITMOV [7 : 4] 0 0 0
Upper : Register name Lower : Default value
Serial Mode Settings
0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0
D0 to D6: DRVPULSE [6 : 0] Operation count setting register. Specify a number from 0 to 127. The number of cyclic operations determined by x are performed. Additional data can be input and data is added up to the equivalent of total of 512 pulses.
D7 0 1 M/I macro
Operation direction switching *Default Infinity distance direction Macro direction
Operation direction switching register The operation count setting register is reset when the register is switched. To stop the operation of the unit, switch the M/I register and set DRVPULSE to 0 for input. This register is also used to set the direction of operation when the initialization sequence is to be performed.
No.A0844-6/12
LV8092GQ
1 0 0 0 0 0 0 0 1 D7 0 0 D4 D3 D2 D1 D0
D0: Register for selecting whether the initialization sequence is to be performed when EN is set high. D0 INIT Initialization to be performed/not to be performed setting 0 Initialization to be performed *Default
1 Initialization not to be performed
D0 0 0 1 1
D1 0 1 0 1
RET 2 times 1 time 3 times 4 times
Number of initialization sequence swing back *Default
D4 0 0 1 1
D3 0 1 0 1
CKSEL 1/4 1/2 1 1
Input clock division ratio switching *Default 1/4 1/2 1 (no frequency division) 1 (no frequency division) Gate mode operation *Default Forward/reverse/braking Forward/reverse/standby
D7 0 1
GATE MODE1 MODE2
2
0
0
0
0
0
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
RST7 to RST0 : Specifies the number of clocks per period (0 to 255). Default = 0 (Internally set to 115 when TEST = H and RESET = L.)
3 0 0 0 0 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0
GTAS7 to GTAS0 : Sets the GATE_A pulse set value (0 to 255). Default = 0 (Internally set to 21 when TEST = H and RESET = L.)
4 0 0 0 0 0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0
GTBR7 to GTBR0 : Sets the GATE_B pulse reset value (0 to 255). Default = 0 (Internally set to 24 when TEST = H and RESET = L.)
No.A0844-7/12
LV8092GQ
5 0 0 0 0 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0
GTBS7 to GTBS0 : Sets the GATE_B pulse set value (0 to 255). Default = 0 (Internally set to 54 when TEST = H and RESET = L.)
RST7-0
GTAS7-0
GATEA GTBS7-0
GTBR7-0
GATEB
6
0
0
0
0
0
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
STP7 to STP0 : Specifies the number of output pulse steps with regard to DRIVE input (1 to 256). Default = 1 The setting value range is handled as the data value plus 1. When data is input in 8-bit units (0 to 255), it is handled as an STP period of 1 to 256. (Internally set to 139=140 periods when TEST = H and RESET = L.)
7 0 0 0 0 0 1 1 1 0 0 0 0 D3 D2 D1 D0
INITMOV7 to INITMOV4 : Sets the number of swing back of the initialization sequence to be performed (16 to 256). Default = 16 (Internally set to 175 when TEST = H and RESET = L.)
D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 INIT7 to 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 to 256 15 31 47 63 79 95 111 127 143 159 175 191 207 223 239 255
No.A0844-8/12
LV8092GQ
Functional Description 1 period : One period of OUT waveform operation is equivalent to one output operation.
Tf = 1 period
EN input : A low-level EN input causes the IC to stop operation, placing the IC in the standby mode to save current consumption. A high-level EN input starts the IC. After performing the initialization sequence according to the predefined startup sequence, the IC starts operation due to DRVPULSE (when the initialization sequence is to be performed). The IC accepts I2C communication whether EN is high or low. Initialization sequence (on or off and direction can be set by I2C) : This is an internal sequence in which the actuator is moved to the initial position when the IC is started up. Setting EN from low to high initiates this initialization sequence. The presence or absence of the initialization operation can be set using the initialization mode select register (INIT). If the initialization operation is specified, the direction of the initialization sequence can be set using the M/I register. * M/I register = 0 : Initialization processing in infinity direction The IC performs the number of operations determined by STP setting period x INIT setting times in the infinite direction, then waits for the period equivalent to STP setting period x 4 times, and performs the number of swing back operations equal to STP setting period x RET setting times in the macro direction. * M/I register = 1 : Auto macro operation in macro direction The IC performs the number of operations determined by STP setting period x INIT setting times in the macro direction, then waits for the period equivalent to STP setting periods x 4, and performs the number of swing back operations equal to STP period setting period x RET setting times in the infinity direction. RESET input : The input pin to reset the internal registers. When it is low, the counter is reset. When it is high the reset state is released. The reset input needs to be held high when I2C communication is in progress. TEST1 pin : This is a setting pin used when the IC is tested. It must be short-circuited to ground when the IC is used in a real application. When this pin is set high, a test counter value is loaded into the internal register, and it can no longer be set in I2C communication. TEST2 pin : This is a setting pin used when the IC is tested. It must be short-circuited to ground when the IC is used in a real application. When this pin is set high, the IC is ready for continuous output operation and continues operation in the infinity direction. BUSY output : This is an output signal pin that is held high (H = VDD voltage) while the actuator is in operation and set low when the actuator is stopped. VDD : This is a power voltage pin for the input pins. It supplies power to the EN, SCL, SDA, and RESET pins. Each input pin is provided with an internal level shifter circuit, so that it is not affected by potential difference from the VCC voltage (the CLK and TEST pins accept input with respect to the VCC voltage level). CLK input : The pin for the external CLK input that provides the reference time for generating drive waveforms. The frequency division ratio for I2C communication can be selected from 1/4, 1/2, and 1/1. Drive waveforms are generated by counting this frequency-divided clk pulses as the basic count unit. The LV8092GQ supports frequency from 10MHz to 60MHz depending on the frequency division ratio and counter settings.
No.A0844-9/12
LV8092GQ
Actuator drive waveform settings : Configuration of piezoelectric actuator drive waveform
f = 1 period
Ta
off
Tb Since the counter starts from zero, a value minus 1 is set. RST = Number of clock pulses in period minus 1 GTAS = Ta + 1 Ta - 1 + 2 = Ta + 1 since the waveforms start after two clock pulses.
Drive parameter settings
Rises here after two clock pulses from reference.
GTBR = GTAS + off
Waveform start reference point
GTBS = GTBR + Tb
The drive waveforms are set using four parameters: RST, GTAS, GTBR and GTBS. RST : Parameter determines the period, and sets the reference clock pulse count minus 1. GTAS : Parameter determines the time taken for the gate signal A to the falling edge from the reference point. Since the signal raises after two clock pulses from the reference, the Ta reference clock cycle count plus 1 is set. GTBR : Parameter determines the time taken for the gate signal B to the rising edge from the reference point. It sets the value obtained by adding the reference clock pulse count during the time from GTAS to "off." GTBS : Parameter determines the time taken for the gate signal B to the falling ewdge from the reference point. It sets the value obtained by adding the reference clock pulse count during the time from GTBR to "Tb." [Example of settings] When setting reference clock to 10MHz, period to 13s, Ta to 2.0s, off to 0.3s, and Tb to 3.0s Since the reference clock time is 0.1s : The period is 130 clks. Specify 129 (RST value of 130 -1). Ta is 20 clks. Specify 21 (GTAS value of 20 + 1). off is 3 clks. Specify 24 (GTBR value of 21 + 3). Tb is 30 clks. Specify 54 (GTBS value of 24 + 30).
No.A0844-10/12
LV8092GQ
Timing charts Enlarged view of the sequence of output signals
(RST setting + 1) x number of clock pulses Operation toward infinity OUT1 (GTAS setting - 1) x number of clock pulses OUT2 (GTBR setting -1) x number of clock pulses Operation toward macro (RST setting + 1) x number of clock pulses (GTBR setting -1) x number of clock pulses OUT1 (GTBS setting - 1) x number of clock pulses OUT2 (GTAS setting - 1) x number of clock pulses (GTAS setting - 1) x number of clock pulses (GTAS setting - 1) x number of clock pulses (GTAS setting - 1) x number of clock pulses
Sequence of initial setting operation ("on" or "off" can be set by the I2C settings.) When M/I register = 00 Movement toward infinity position
Startup when EN is high, initial setting sequence starts EN
1 period OUT1 OUT2 Operation toward infinity STP period x INIT times Standby state Operation toward macro STP period x 4 STP period x RET setting times
Initial setting operation time BUSY High during initial setting in wait state too BUSY output is low after initial setting. BUSY output is high during initial setting operation.
When M/I register = 01 Movement toward macro position
Startup when EN is high, initial setting sequence starts EN
OUT1 OUT2
1 period
Operation toward macro STP period x INIT times
Standby state
Operation toward infinity
STP period x 4 STP period x RET setting times
Initial setting operation time BUSY High during initial setting in wait state too BUSY output is high during initial setting operation. BUSY output is low after initial setting.
No.A0844-11/12
LV8092GQ
Sequence of operations triggered by DRVPULSE input
EN M/I register state Infinity direction logic selection Operation stops when EN input is low. Macro direction logic selection
DRVPULSE setting
I2C communication operation instruction completed 00000000_10000010 (operation 2 times toward macro) Equivalent to 2 pulses = STP setting period x operation for 2 times 1 period Operation toward infinity (STP setting period x 2 times) I2C communication Operation starts on completion of DRVPULSE input. Operation toward macro
I2C communication operation instruction completed 00000000_00000010 (operation 2 times toward infinity)
OUT1 OUT2
BUSY
Return to high when EN is set to low even before the completion of the operation.
BUSY output high, only during operation period
Gate setting output logic
1 period GATE MODE1 : Forward, Braking, Reverse OUT1 Braking Braking OUT2 Reverse 1 period GATE MODE2 : Forward, Wait, Reverse OUT1 Wait OUT2 Reverse Wait Forward Forward OUT1 on on OUT1 off on on off OUT2 OUT1 on off Forward Forward Output mode off on OUT2
Forward off off OUT2 OUT1
Reverse off off OUT2 off off
Braking
Wait
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This catalog provides information as of August, 2007. Specifications and information herein are subject to change without notice. PS No.A0844-12/12

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